Mitel MT90840 Instrukcja Użytkownika Strona 1

2-231Features• Time slot interchange function between eightpairs of ST-BUS/GCI/MVIP streams (512channels) and parallel data port• Programmable data

MT90840 Preliminary Information2-240Register enables the internal divider, and the SPCKooutput (and internal 4.096 MHz clocks) are driven bythe clock

Preliminary Information MT908402-241streams, and trigger the PPCE interrupt bit. PPCEwill be triggered by PPFRi moving from the expectedtime, but PPCE

MT90840 Preliminary Information2-242TM1. This allows for flexible round-trip data delays instar or ring type networks. An elastic buffer on thereceive

Preliminary Information MT908402-243The transmit path does not provide an elastic buffer,and therefore the serial port clock must be tightlylocked (in

MT90840 Preliminary Information2-244Timing Mode 3 (TM3) - Bus SlaveSynchronous Parallel Port With ST-BUS ClockSlaveTiming Mode 3 is used where the mai

Preliminary Information MT908402-245Timing Mode 4 (TM4) - Parallel Data SwitchingTiming Mode 4 is used to provide switching of up to2430 parallel inpu

MT90840 Preliminary Information2-246Table 1 - MT90840 Throughput Delay SummaryNaming rules:ELD: ELastic Delay, measured from PPFRi to F0i (4.4 to 129.

Preliminary Information MT908402-247TPCM High location is output on the correspondingCTo pin once every frame. See Figure 9. The controloutputs can be

MT90840 Preliminary Information2-248all 16 serial streams can be individually controlled,so that up to 512 channels can be either transmittedor receiv

Preliminary Information MT908402-249Figure 12a - 2.048 Mbps Add/Drop Mode TPDMAddressingFigure 12b - 2.048 Mbps Add/Drop Mode RPCMAddressing4.096 Mbps

MT90840 Preliminary Information2-232Figure 2 - Pin ConnectionsNCNCNCNCNC745658606264687072661228262422181614203230541086428482807876343638404244464850

MT90840 Preliminary Information2-250Figure 14a - 8.192 Mbps TPDM AddressingFigure 14b - 8.196 Mbps RPCM AddressingMicroprocessor PortAn 8-bit multiple

Preliminary Information MT908402-251short, or a signal contention, prevents the DTA pinfrom reaching a valid logic HIGH, it will continue todrive for

MT90840 Preliminary Information2-252the DTA pin will be asserted (as the data is stored inthe write-pipeline) but the next CPU access will notsee DTA

Preliminary Information MT908402-253DR1-0 and FDC in the IMS register) beforeprogramming the RPCM.b) The GPM Register is written. The CPU sets theBloc

MT90840 Preliminary Information2-254I/O pin of the IC. The operation of the boundary-scancircuitry is controlled by a Test Access Port (TAP)Controller

Preliminary Information MT908402-255Test Data RegistersAs specified in the IEEE 1149.1 Standard, theMT90840 JTAG interface contains two test dataregist

MT90840 Preliminary Information2-256Register DescriptionInterface Mode Selection Register (IMS) - READ/WRITE76543210DR1 DR0 PPS1 PPS0 ODE 0 0 FDCDR1-0

Preliminary Information MT908402-257General Purpose Mode Register (GPM) - READ/WRITE76543210BPD6 BPD5 BPD4 PPFP SPFPBPD7 DIN BPEBPD7-4 Block-Programmi

MT90840 Preliminary Information2-258This register selects which 128 byte page of which internal memory will be accessed by the CPU when the address bi

Preliminary Information MT908402-259Internal Memory DescriptionOE/CTo0 Output Enable. Provides per channel tristate control on the parallel port side.

Preliminary Information MT908402-233Pin DescriptionPin #Name Description84 100343DS/RD Data Strobe/Read (Input). In Motorola multiplexed-bus mode this

MT90840 Preliminary Information2-260MC Message Channel: The message channel contents are provided by the CPU in bits AB0-7 in the Rx Path ConnectionMe

Preliminary Information MT908402-261ApplicationsDistributed Isochronous NetworkLow latency isochronous backbones provide for thedeployment of systems

MT90840 Preliminary Information2-262synchronization scheme may be used in applicationssuch as the proposed MVIP multi-chassis level 3interface (MC-3 s

Preliminary Information MT908402-263AC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.Characteristics

MT90840 Preliminary Information2-264‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.Fig

Preliminary Information MT908402-265Figure 18 - Serial Port Timing for 2.048 Mbps Operation - TM2 (SFDi = 1) and TM1C4/8R1tfrwSTi0-7STo0-7(4.096 MHz)b

MT90840 Preliminary Information2-266Figure 19 - Serial Port Timing for 2.048 Mbps - TM2 (SFDi = 0) and TM3tsodSTo0-7SPCKo(4.096 MHz)STi0-7tstiststihF0

Preliminary Information MT908402-267Figure 20 - Serial Port Timing for 4.096 Mbps Operation - TM2 (SFDi = 1) and TM1STo0-7C4/8R1(4.096 MHz)STi0-7F0i i

MT90840 Preliminary Information2-268Figure 21 - Serial Port Timing for 4.096 Mbps Operation - TM2 (SFDi = 0) and TM3STo0-7SPCKo(4.096 MHz)STi0-7F0o ou

Preliminary Information MT908402-269Figure 22 - Serial Port Timing for 8.192 Mbps - TM1 and TM2 (SFDi = 1)Figure 23 - Per-Channel Tristate Characteris

MT90840 Preliminary Information2-23422 66 F0i/o Serial Port Frame Synchronization (Bidirectional). This 8 kHz frame pulsesignal indicates the TDM 125

MT90840 Preliminary Information2-270Figure 24 - Serial Port Timing for 8.192 Mbps - Timing Modes 2 and 3STo0-7C4/8R1**(8.192 MHzSTi0-7F0o outputbit 0,

Preliminary Information MT908402-271Figure 25 - Timing for the Parallel Port External Control Lines CTo0-3Figure 26 - TM1 Parallel Port Transmit Timin

MT90840 Preliminary Information2-272Figure 28 - Parallel Port Receive Timing‡ Typical figures are at 25°C and are for design aid only: not guaranteed a

Preliminary Information MT908402-273Figure 29 - Parallel Port in Timing Mode 4Figure 30 - Phase Variation Between C4/8R1 & C4/8R2 and PCKT Inputs

MT90840 Preliminary Information2-274† Timing is over recommended temperature & power supply voltages.‡ Typical figures are at 25°C and are for desi

Preliminary Information MT908402-275Figure 32 - Intel/National Multiplexed Bus TimingALEAD0-AD7CSRDWRDTAtalwtadstadhDATAADDRESStalrdtcsrwtdhrtdhwtcswt

MT90840 Preliminary Information2-276† Timing is over recommended temperature & power supply voltages.‡ Typical figures are at 25°C and are for desi

Preliminary Information MT908402-277Figure 33 - Motorola Multiplexed Bus TimingCSDTAAD0-13RDDSR/WASADDRESSADDRESSDATADATAtrwhtrwstaswtdshtadstadhtdhwt

MT90840 Preliminary Information2-278Figure 34 - Boundary Scan Test Port TimingFigure 35 - RESET TimingAC Electrical Characteristics - Boundary-Scan Te

Preliminary Information MT908402-279Figure 36 - 84 PLCC Mechanical DrawingFigure 37 - 100 Pin PQF Mechanical DrawingFD1DHE1IA1AGD2EE2Dim Min MaxA0.165

Preliminary Information MT908402-23559 10 TRST Test Reset (Input). Asynchronously initializes the JTAG TAP controller, placing itin theTest-Logic-Rese

MT90840 Preliminary Information2-280Notes:

MT90840 Preliminary Information2-236Functional DescriptionThe MT90840 Distributed Hyperchannel Switch is alarge switching, multiplexing, and rate-adap

Preliminary Information MT908402-237Figure 3 - Serial Port Interface Functional TimingFigure 4 - Parallel Data Port Functional TimingC4/8R1&2Seria

MT90840 Preliminary Information2-238an address-value in the path’s Data Memory. A givenoutput time slot is controlled by programming theConnection Mem

Preliminary Information MT908402-239programmed to switch parallel inputs to paralleloutputs. For each parallel output channelcontrol-address, the Tx P